A memory cell structure, in which one switching transistor is combined with one capacitor, has been known. For example, such a memory cell structure is formed at the same time with a logic transistor structure and, thereby, a semiconductor memory-merged logic large scale integration (LSI) is produced.
As for a capacitor of a logic-in-memory cell, a capacitor having a structure, in which a cell plate electrode and a semiconductor substrate are disposed oppositely with a capacitor insulating film therebetween, an inversion layer is formed on the semiconductor substrate surface because of a voltage applied to the cell plate electrode, and the resulting inversion layer serves as a charge accumulation region, is used.
Furthermore, an element isolation insulating film of a shallow trench isolation (STI) is dug, and a cell plate electrode is formed entering an element isolation groove, so that active regions of element isolation groove side walls are used as charge accumulation regions and, thereby, the capacity is increased (1TQ structure).
An impurity diffusion layer (storage diffusion layer) on the capacitor side of a switching transistor of the memory cell is connected to the inversion layer of the capacitor and serves as a part of the charge accumulation region. In order to improve the charge retention characteristic of the memory cell, it is desirable to reduce a leakage current through the storage diffusion layer, for example, a junction leakage current. In this regard, if the temperature becomes high (for example, 125° C.), a leakage current through the storage diffusion layer increases significantly.
Consequently, it is difficult to produce a memory cell, in which a leakage current through the storage diffusion layer is suppressed.